The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for forming a pattern in a semiconductor device.
When forming a gate pattern in a dynamic random access memory (DRAM), it is often required to further reduce a critical dimension (CD) of a peripheral region to form a high-speed device.
FIGS. 1A and 1B illustrate cross-sectional views of a typical method for forming a semiconductor device.
Referring to FIG. 1A, a polysilicon layer 102 and a nitride-based layer 103 for forming a gate hard mask are formed over a substrate 101 including a cell region and a peripheral region. Photoresist patterns 104A and 104B are formed over the nitride-based layer 103. The photoresist pattern 104A is formed in the cell region and the photoresist pattern 104B is formed in the peripheral region, exposing pattern regions. Hereinafter, the photoresist pattern 104A in the cell region is referred to as the first photoresist pattern 104A and the photoresist pattern 104B in the peripheral region is referred to as the second photoresist pattern 104B.
Referring to FIG. 1B, the nitride-based layer 103 is etched. Reference numerals 103A and 103B refer to a first etched nitride-based layer 103A remaining in the cell region and a second etched nitride-based layer 103B remaining in the peripheral region, respectively. In the typical method, gate patterns are formed by forming the first and second photoresist patterns 104A and 104B exposing the pattern regions in the cell region and the peripheral region and performing the etch process using the first and second photoresist patterns 104A and 104B.
In the typical method, the first etched nitride-based layer 103A obtains a vertical profile. In contrast, the second etched nitride-based layer 103B obtains a sloped profile as represented with reference denotation ‘S’, causing an enlarged CD of the gate pattern in the peripheral region. The sloped profile is formed because a difference exists in pattern densities between the cell region and the peripheral region, and a loading effect is generated in the peripheral region where a spacing distance is large between patterns, causing polymers generated while etching the nitride-based layer 103 to accumulate on sidewalls of the second etched nitride-based layer 103B.
CD targets in the cell region and the peripheral region may not both be satisfied because the gate patterns are formed by performing one mask process on the cell region and the peripheral region. Also, it may be difficult to reduce the size below a certain level due to diverse pattern forms in the peripheral region.